View E-L6452_8324911.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev 2 february 2006 1/22 22 l6452 dual 13x16 matrix head ink jet driver features drives two 13x16 matrix heads head temperature sensing power up system electrical nozzle check 8 bit a/d 5 bit d/a 4kv esd protected outputs description l6452 is a device designed to drive two 13x16 matrix ink jet print heads in printer applications. the output stage is able to source simultaneously 400 ma on each of the 16 power lines (columns) with a duty cycle of 33% in normal printing and 66% in head pre-heating. on the address lines (rows), the load is only capacitive (mos fet driving capability). the driver can control two print heads, but only one is active at a time. the address scanning counter is included and can be disabled to allow a different scanning scheme. in order to avoid output activation during the supply transient, an internal power-up system is implemented. as supporting function, l6452 is capable of sensing the head silicon temperature and to electrically check each nozzle. the device is also integrating a thermal protection . order codes pqfp100 part number op. temp range, cpackage packing E-L6452 0 to 70 pqfp100 tray l6452die8 0 to 70 die -- www.st.com
contents l6452 2/22 contents 1 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.3 counter truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 decoder truth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 print head temperature control pa rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 print head block diagram ( figure 5. ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
l6452 block diagrams 3/22 1 block diagrams figure 1. block diagram figure 2. block diagram: power line output stage. print head driver print head temperature control power & logical supplies control lines a/d & print head temperature control lines analog inputs print head a print head b d97in523 13 address lines channel b 16 power lines 13 address lines channel a ncen trigger longpulse shortpulse data bit 15 data bit 1 data bit 0 1 0 ncout output15 output1 output0 va d97in525b 1.25ma from 16 bit data latch
block diagrams l6452 4/22 figure 3. block diagram: nozzle activation part 16 bit serial input & parallel output 16 bit latch 16 power output stages output0 output1 output2 output3 output4 output5 output6 output7 output8 output9 output10 output11 output12 output13 output14 output15 ncout sdi sdc latchclear latchdata ncen longpulse shortpulse selector 4 to 13 lines decoder 13 mos drivers channel a hsa1 enic s3 upc/s2 resc/s1 clkc/s0 hsa2 hsa3 hsa4 hsa5 hsa6 hsa7 hsa8 hsa9 hsa10 hsa11 hsa12 hsa13 13 mos drivers channel b hsb1 hsb2 hsb3 hsb4 hsb5 hsb6 hsb7 hsb8 hsb9 hsb10 hsb11 hsb12 hsb13 c0 c1 c2 c3 0 to 13 up/down counter chsel ench d97in524a
l6452 pin description 5/22 2 pin description figure 4. pin connection (top view) table 1. pin function pin # name function 1 crlatch a rising edge transfer the informat ion from cr shift register into the control register latching the data on the falling edge 2, 5, 6, 8, 9, 11, 12, 14, 16, 18, 19, 21, 22, 24, 25, 28 output15...0 high side dmos outputs. to be active, shortpulse and/or longpulse and ncen must have a low level 1 2 3 5 6 4 7 8 9 10 36 11 37 38 39 40 41 95 94 93 92 90 91 89 88 87 86 85 70 69 68 66 65 67 75 74 73 71 72 output13 output14 powgnd output15 crlatch v c output10 v c output11 v c output12 reset convstart adck ncout addata ch0buf analognd adcgnd v a vref ch5 rxa rxb rext csgnd v a v dd vstep-up stepupboost stepupgnd clkc/s0 ench hsa4 hsa5 hsa6 hsa8 hsa9 hsa7 enic gnd hsa1 hsa3 hsa2 d97in489c 96 vxa 97 vxb 98 onenable 99 crclock 100 crdata latchdata sdi sdc longpulse shortpulse 31 32 33 34 35 64 63 61 60 62 hsa10 hsa11 hsa13 v r hsa12 12 13 14 15 16 output7 powgnd output8 output9 v c 17 18 19 20 v c output5 output6 v c 21 22 23 24 25 output1 output2 v c output4 output3 59 57 56 58 hsb13 hsb11 hsb10 hsb12 hsb9 hsb8 hsb6 hsb5 hsb7 45 46 47 48 49 50 84 83 81 82 ch4 ch3 ch1 ch2 resc/s1 upc/s2 chsel s3 42 43 44 26 27 28 29 30 ncen latchclear output0 v c powgnd 55 54 52 51 53 hsb4 hsb3 hsb1 gnd hsb2 80 79 78 76 77
pin description l6452 6/22 3, 7, 10, 13, 17, 20, 23, 26 vc outputs power supply 4, 15, 27, 51, 79, 92 gnd logic and power ground 29 latchclear a high level resets all bit in the latch 30 ncen a high level enables the internal current sources and disables all dmos outputs. to be active, the internal current sources must have their corresponding bit set in the 16 bit latch and longpulse must be set to low level. this function is called nozzle check enable. 31 latchdata a rising edge latches the 16 bit stored in the shift register in the 16 bit latch 32 sdi serial data input of the shift register 33 sdc the data bit presented to the sdi pin is stored into the register on the rising edge of this pin 34 longpulse a low level activates all outputs having their corresponding bit in the 16 bit latch set (this pin has an internal pull-up resistor) 35 shortpulse a low level activates all outputs having their corresponding bit in the 16 bit latch reset (this pin has an internal pull-up resistor) 36 reset a low level disables all functions and clears all registers 37 convstart a high level enables the a/d to start the new conversion 38 adck a/d clock signal; the addata signal are valid on the falling edge of this pin 39 ncout if ncen is high this output provides a high level when the open load is detected on the output. if ncen is lo w this output provides a high level when a short circuit is detected on hsa/b output 40 ch0buf analog output signal (ch0 buffered) 41 addata a/d serial data output 42 analoggnd analog ground connection 43 adcgnd ground of internal adc 44, 90 va power supply 45 vref reference voltage generator 46 to 50 ch5..ch1 a/d input signals 52 to 64 hsb1..hsb13 head selector address output channel b 65 vr head select power supply 66 to 78 hsa13..hsa1 head selector address output channel a 80 enlc enable internal counter: a high level enables the counter and the internal decoder will activate of the hsx outputs according to th e counter?s outputs. signal s0 becomes clkc and s1 becomes resc table 1. pin function - continued pin # name function
l6452 pin description 7/22 81 chsel channel select: a low level enables channel a and a high level enables channel b 82 s3 decoder input signals when enic is low 83 upc/s2 upcount/s2: a high level enables the internal counter to up counting. a low level enables down counting depending on enlc value it becomes s2. 84 resc/s1 reset count/s1: a low level resets the internal counter depending on enlc value it becomes s1. 85 ench enable channel: a low level enables the selected channel (this input has an internal pull up resistor) 86 clkc/s0 a high level clocks the internal counter depending on enlc value it becomes s0. 87 stepupgnd ground of step up block 88 stepupboost boost voltage 89 vstepup driving voltage of power dmos stage 91 vdd 5v logic supply 93 rext an external resistor connected to ground fixes the internal current source value 94, 95 rxb, rxa current source outputs 96, 97 vxa, vxb rxa, rxb voltage after an optional external filter 98 onenable a low level enables the current source generator according the a /b and on/ o ff control register bit 99 crclock data on pin crdata are stored into the register on the rising edge of this pin 100 crdata control register serial data input table 1. pin function - continued pin # name function
electrical specifications l6452 8/22 3 electrical specifications 3.1 absolute maximum ratings table 2. absolute maximum ratings 3.2 dc electrical characteristics symbol parameter value unit v c power line supply voltage 14 v v r address line supply voltage 14 v va analog supply voltage 14 v v dd logic supply voltage 6 v v step_up driving voltage of power dmos stage 28 v esd in accordance with iec 1000-4-2 (1) (1) all the pins connected to the pen passed esd contact electrostatic discharge @ 4kv (150pf, 330ohm source). 4 kv v in logic input voltage range -0.3 to v dd + 0.3 v i out output continuous current 0.5 a t j junction temperature 150 c t amb operating temperature range 0 to 70 c t stg storage temperature range -55 to 150 c table 3. dc electrical characteristics (t j = 25c) symbol parameter test cond ition min. typ. max. unit v c power line supply voltage (1) 10.5 (2) 11.5 12.5 v v r address line supply voltage (1) 10.5 11.5 12.5 v v a analog supply voltage (1) 10.5 11.5 12.5 v v dd logic supply voltage 4.5 5 5.5 v i cs v c sleep supply current onenable = 1 reset = 0 1 ma i rs v r sleep supply current 0.3 ma i as v a sleep supply current 3 ma i c v c supply current 1.5 ma i r v r supply current 0.6 ma i a v a supply current i rext = 3ma 13 ma
l6452 electrical specifications 9/22 i dd v dd supply current sleep or normal condition 5 ma v ref reference voltage t amb = 5 to 55c 4.85 5 5.15 v i refext reference current (external) 7 ma i ccs programmed constant cu rrent 12 13.5 ma i ccs /i ccs constant current regulation v a =11v t amb = 5 to 55c 0.33 % v ampout output voltage of integrated e (3) va-1 v amplifier v cm operating input voltage at pins v ref = 5v g1=1.2 g2 = 3 7 v vxa and vxb g1 amp. a1 voltage gain 1.188 1.2 1.212 g2 amp.a2 voltage gain 2.95 3.02 3.10 v step-up driving voltage of power dmos vc +11 v a/d converter v a/d in a/d input voltage selected channel: ch1 to ch5 selected ch=ch0 0 e (3) vref vref v v i exch a/d input current input ch1 to ch5 selected or not 1 a offset voltage generation / dac v offset offset voltage v ref = 5v 2.5 + e (3) 7.34 v v step voltage increment (1lsb) v ref = 5v 156 mv k dac voffset/vref any step n 4 3 % a/d converter timings t cscks convstart set up time 200 ns t csckh convstart hold time 200 ns t ckout falling edge of clock to data out valid delay c load 20pf 200 ns t csz convstart falling edge to output in hi-z delay 200 ns f adck clock frequency 250 khz t cslow conv. start low level time 5.6 s table 3. dc electrical characteristics (t j = 25c) - continued symbol parameter test cond ition min. typ. max. unit i ccs v ref 2r ext --------------- 4 ? =
electrical specifications l6452 10/22 t acqth theoretical acquisition time f adck = 250 khz 32.4 s t acqpr real acquisition time f adck = 250 khz 36 s digital interface input v inp schmitt trigger positive-going threshold 2/3v dd v v inm schmitt trigger negative-going threshold 1/3v dd v v hys schmitt trigger hysteresis 0.1 0.3 1 v i in input current (vin=0; v dd =5) (4) 50 150 300 a cr latch timings t ls latch set up time 100 ns t lhigh latch high time 100 ns t lconv latch data valid to a/d input valid delay selected channel: ch1..ch5 ch0 4 7 s s t store latching data time 200 ns note: the control register (driving signals crdata, crclock) is accessed with the same timing specifications as the data 16 bit shift register (signals sdi, sdc) shift register and latch timing t a set up time 35 ns t b hold time 35 ns t c serial clock low time 35 ns t d serial clock high time 35 ns t e serial clock period 125 ns t f latch set up time 100 ns t g latch data high time 100 ns t set ncen setup time with respect to longpulse (or shortpulse ) asserted 160 ns t hold ncen hold time with respect to longpulse (or shortpulse ) asserted 0ns t lp set-up time from latch to pulse (short and long) 125 ns t pl time from pulse deassertion to new data latching 125 ns table 3. dc electrical characteristics (t j = 25c) - continued symbol parameter test cond ition min. typ. max. unit
l6452 electrical specifications 11/22 outputs electrical characteristics i out output current (outputs 0..15) dc=33%; preheating dc=66% 400 ma r ds(on) on resistance t j = 25c 1.3 t pdr power output turn on time from 50% longpulse to 90% power output rising edge load = 30 ohm in parallel with 1.5nf 160 ns t pd toff delay time from 50% longpulse to 90% power output falling edge load = 30 ohm in parallel with 1.5nf 100 ns r pon open nozzle check 0.5 1 2 k head address selector output t h upc/s2, resc/s1, chsel, clkc/s0 and enic set-up time with respect to ench 150 ns t k upc/s2, resc/s1, chsel, clkc/s0 and enic hold time with respect to ench 50 ns t j upc/s2 with respect to hold time clkc/s0 200 ns t i upc/s2 with respect to setup time clkc/s0 100 ns t m enable input to active output delay time 100 ns t n clock to active output delay time 150 ns t o disable input to inactive output delay time 100 ns f clk-counter counter clock frequency 1 mhz clk dc clock duty cycle 10 90 % t on address turn on time from 50% clkc/s0 or selector signal to 90% of the address output variation load: see figure 11. 325 ns t off address turn off time 325 ns (1) the three supply voltage are i ndependent inside the specified value; (2) the min. value for v c power line has been verified down to 4v in applic ation lab.; nevertheless the parameters are guaranteed within spec limit of the above dc electrical characteristics table. (3) e = 2 v step (4) this applies to input pins having an internal pull-up (ench, longpulse , shortpulse ) table 3. dc electrical characteristics (t j = 25c) - continued symbol parameter test cond ition min. typ. max. unit
electrical specifications l6452 12/22 3.3 counter truth table enic = 1 upc/s2 = 1 resc/s1 = 1 enic = 1 upc/s2 = 0 resc/s1 = 1 clock counter c3 c2 c1 c0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 0 11 0 0 11 0 1 11 1 1 11 1 0 10 1 0 10 0 0 0 0 0 0 clock counter c3 c2 c1 c0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 0 1 1 1 0 1 1 0 0 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0
l6452 electrical specifications 13/22 3.4 decoder truth table * c3 = s3, c2 = s2, c1 = s1, c0 = s0, when enic = 0 this table is valid for both channel a and channel b and when ench is set to low level. outputs (hs) active c3* c2* c1* c0* all inactive 0 0 0 0 1 0 0 0 1 2 0 0 1 1 3 0 0 1 0 4 0 1 1 0 5 0 1 1 1 6 0 1 0 1 7 0 1 0 0 8 1 1 0 0 9 1 1 0 1 10 1 1 1 1 11 1 1 1 0 12 1 0 1 0 13 1 0 0 0 all inactive 1 0 0 1 all inactive 1 0 1 1
print head temperature control part l6452 14/22 4 print head temperature control part 4.1 introduction for quality printing, it is necessary to know and control the temperature of the print head. thus, the latter has a built - in aluminium resistor, whose value changes slightly with the temperature. the temperature determination is done by injecting a constant current in the resistor, and measuring the voltage drop across it. since high - end printers have two heads, it must also be possible to switch quickly the measurement process from one to the other. the function is foreseen to be integrated into the head driver, and is described hereafter. 4.2 print head block diagram ( figure 5. ) at first we have a constant current source, which can be disabled by an external pin ( onenable ) or by a control register, described later. the value of the current can be programmed by an external resistor, and is given by: this current is injected either into the resistor of the head a (ralu. a) or b (ralu. b), depending of the switch sw3. the resistors are grounded, and the voltage at their << hot >> side (vx) is re-entered via the pins vxa and vxb. using s eparate pins from rxa and rxb permits to be more flexible, and a filter can eventually be added as shown in the drawing. the voltage vx is amplified by a1 and a2, and then converted in a digital value. to be compatible with the input range of the a/d converter, it is necessary to subtract an offset voltage voffset from vx. moreover, as the initial value of the aluminum resistor is very imprecise. voffset must be adjustable; this is done by means of a 5 bit - d/a converter, giving 32 different values. finally, the voltage at the input of the a/d converter is: v ch0 = g1 g2 vx - g2 v offset or v ch0 = g1 g2 ralu i ccs - g2 v offset ; v offset = v ref /2 + n v ref /32 n = 0, 1, ...31 the reference voltage generator (v ref ) is integrated, and used for the current source and both the a/d and d/a converters. in this way, the system performance is independent from the precision of v ref ; this one should, however, be stable. vref is also available on pin #45, and can be used for low consumption purposes. (the external sinked current has to be a dc current). the system is under control of a 10 bit register, cr. cr is accessed serially and has a transparent latch, which can be used or not (by trying the latch signal cr latch to v cc ). i ccs v ref 4 ? 2r ext ? ---------------------- =
l6452 print head temperature control part 15/22 figure 5. print head block diagram figure 6. control register details. ref volt vref + g1 a1 g2 a vref/2 vref out va d/a 5 bit a/b on/off da4 da3 da2 da1 da0 addr2 addr1 addr0 d vref control register latch 10 bit shift reg. 10 bit crlatch crclock crdata a b d c vref a2 vx sw1 sw2 sw3 ch0 + - ch1 ch2 ch3 ch4 ch5 addata adck convstart a/d inputs ch0buf rext onenable rxa, rxb vxa, vxb ralu b ralu a analog gnd note; the analog ground is separated from the digital ground of the remaining part of the driver d97in533c high-side constant current source voffset a/b on/off da4 da3 da2 da1 da0 addr2 addr1 addr0 d/a inputs for offset compensation d97in534b cr9 cr8 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 channel selection a/d input shift direction selection of resistor a (a/b = 0) or b (a/b = 0) for temperature measurement switches the current source on or off; linked with onenable input pin on/off onenable action 0 1 0 1 1 1 0 0 off off off on addr2 channel address ch0buf 0 0 0 0 0 (internal) 1 (external) 2 (external) 3 (external) a b b b one internal channel (vx measurement) five uncommitted, genral-purpose external channels addr1 0 0 1 1 addr0 0 1 0 1 1 1 0 0 0 1 4 (external) 5 (external) b b c d da0 = lsb da4 = msb positive logic 110 6 111 7
print head temperature control part l6452 16/22 figure 7. cr latch timings figure 8. a/d converter timings figure 9. power output timing figure 10. trigger of nozzle check signal t lconv t lhigh t store t ls convstart crlatch crclock crdata d97in535b da0 addr2 addr1 addr0 t csx t cscks adck addata d97in536 65 4 2 731 0 high impedance convstart high impedance t csckh t ckout 50% 50% 90% 90% longpulse or shortpulse power output d97in526b t pdr t pd (*) (*) t pd does not include the falling edge time because this is strictly dependent on the rc load. + - internal reference 1 0 ncen v power v logic nozzle check output from the common connection of analog multiplexers hsa/b short circuit detection d97in527a
l6452 print head temperature control part 17/22 figure 11. address load reference figure 12. mode counter hs output 200 a 250pf t o t k t i t j t h t m t n hsa1 : 13 or hsb1 : 13 ench clkc/s0 enic chsel resc/s1 upc/s2 d97in529b
print head temperature control part l6452 18/22 figure 13. mode selelector figure 14. sequence of shift register data loading t o t k t h t m t n hsa1 : 13 or hsb1 : 13 ench enic chsel sel 0:3 d97in530a d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d0 sdi sdc latchdata longpulse shortpulse output * output ** * the corresponding data bit is set ** the corresponding data bit is reset d97in531c t pl t lp
l6452 print head temperature control part 19/22 figure 15. latch timing t c t g latchdata sdck sdi d97in532a t a t b t d t e t f
package information l6452 20/22 5 package information in order to meet environmental requirements, st offers these devices in ecopack ? packages. these packages have a lead-free second level interconnect. the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com. figure 16. pqfp100 mechanical data & package dimensions pqfp100 dim. mm inch min. typ. max. min. typ. max. a 3.40 0.134 a1 0.25 0.010 a2 2.55 2.80 3.05 0.100 0.110 0.120 b 0.22 0.38 0.0087 0.015 c 0.13 0.23 0.005 0.009 d 22.95 23.20 23.45 0.903 0.913 0.923 d1 19.90 20.00 20.10 0.783 0.787 0.791 d3 18.85 0.742 e 0.65 0.026 e 16.95 17.20 17.45 0.667 0.677 0.687 e1 13.90 14.00 14.10 0.547 0.551 0.555 e3 12.35 0.486 l 0.65 0.80 0.95 0.026 0.031 0.037 l1 1.60 0.063 k 0 (min.), 7 (max.) outline and mechanical data
l6452 revision history 21/22 6 revision history date revision changes 15-mar-1999 1 initial release. 06-feb-2006 2 modified electrical specification and any time diagrams. modified pin and signal names through out the spec. modified ta bl e 1 pin function pins 83, 84 & 86. added esd parameter in the ta b l e 2 absolute maximum ratings. modified ta bl e 3 : t set , t hold and r pon parameters. modified figure 14 .
l6452 22/22 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of E-L6452

	To Download E-L6452 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .